1. Field of the Invention
This invention relates in general to electronic circuits, and more particularly, to dynamic set/reset circuits used within semiconductor logic devices, memory, or processors.
2. Relevant Background
In the design of semiconductor logic, memory, or processors/microprocessors, integrated circuit designers utilize a number of basic circuit designs as building blocks for implementation of various logic structures within the integrated circuit. For example, dynamic set/reset circuits are used as logic circuits, or in memory or processors for storing a value and then clearing or resetting the value during a time period or cycle.
A conventional dynamic set/reset circuit is shown in FIG. 1A. A normal sequence of operations would involve providing the circuit with a data input, evaluating the data in the circuit (i.e., providing stable data at the output), and then resetting the circuit with a reset signal so that the circuit will be ready for a new data input on the next cycle. Transistor 20 receives the data input, while transistor 22 receives the reset signal. Transistor 20 accepts an active high data input at its gate and provides a logic high level at the output 24, through inverter I1, if the input to transistor 22 is inactive. Inverter I2 is used to maintain the state of the signal at the evaluate node, labeled "EVAL" in the figures, when both inputs are inactive. Upon the input to transistor 20 going low, an active low signal applied to the gate of transistor 22 will reset the output. In order to ensure that stable data is provided at the output to overcome temperature variations or other adverse conditions, the width of the data pulse or the reset pulse can be enlarged. This is typically referred to as margin checking. However, by widening the pulses, the overall cycle time of the circuit is increased which makes such a design undesirable for high-frequency applications.
FIG. 1B shows the circuit of FIG. 1A with a single feedback line used to improve the frequency of the circuit. Assuming that the input signal 46 is low, whenever the RESET line 30 goes high, the output of the transistor 32, shown as the EVAL signal 40, goes high and the feedback signal 34, shown as FB, goes low and maintains a low input to the NAND gate 36, which inactivates transistor 32. The state of the EVAL node is now maintained high through inverters I1 and I2 and the feedback circuit. In this manner, the single feedback can be used to reduce the required pulse width of the RESET signal, and improve the frequency of the set/reset circuit.
While the circuit of FIG. 1B improves the circuit's frequency, one possible problem with the circuit shown in FIG. 1B is that the circuit could experience multiple resets if the timing of the externally provided reset input is not well controlled, possibly resulting in functional failure or improper operations of the circuit.
FIG. 1C show a timing diagram for the circuit shown in FIG. 1B illustrating one scenario where multiple resets occur from a wide reset pule. The cycle begins on a rising edge of the active high RESET signal where the input signal IN is low. The PC.sub.-- 1 signal, being the output of the NAND gate 36, goes low and turns on the transistor 32 which sets the EVAL signal 40 high. The OUTPUT signal 42 then goes low, as does the FB feedback signal 34. Since the FB signal 34 input to the NAND gate 36 is low, the PC.sub.-- 1 signal 44 goes high.
When the IN input signal 46 is asserted high while the RESET signal 30 is high, the transistor 38 turns on which sets the EVAL signal 40 low and the OUT output signal 42 high. The FB feedback signal 34 then goes high, which sets the PC.sub.-- 1 signal 44 back to low since the inputs to the NAND gate 36 are both high.
The problem is that the feedback signal should not change state again until after another rising edge of the RESET signal (i.e., the circuit reset should occur only once per cycle while the RESET signal is high). The multiple reset problem occurs in the circuit of FIG. 1B when the RESET pulse is still active while data is placed in the input 46 and the circuit evaluates the data at the input pin 46. Since the FB signal is high and the RESET signal is high, the PC.sub.-- 1 signal 44 changes state to a logic low which turns on the transistor 44 and begins to pull the EVAL signal 40 high and the OUT signal 42 low. The FB signal 34 then also begins to go low. However, the IN input signal 46 is being externally driven high which turns the transistor 38 on and tends to pull the EVAL signal 40 low. Hence, there is a "collision" since the EVAL signal is being pulled low by the transistor 38 while the transistor 32 pulls EVAL high. The effect of the multiple reset problem is that the pulse width of the OUT output signal 42 is erroneously reduced, which could cause a erroneous data to be read from the set/reset circuit shown in FIG. 1B.
A similar problem involving multiple evaluates can occur in a set/reset circuit if a set input line has a pulse width too wide. The circuit may evaluate the input data twice during a single cycle, which may be problematic.
What is needed is a dynamic set/reset circuit for high-frequency applications which protects against multiple resets or multiple evaluates of the circuit whenever an input reset pulse, or an input set pulse, is unexpectedly wide in pulse width. It is with the shortcomings of the existing art in mind that the significant improvements and advancements of the present invention were developed.